1. Field of the Invention
The present invention relates to a sample-and-hold circuit and a pipeline analog-to-digital converter.
2. Description of the Related Art
A sample-and-hold (S/H) circuit is a circuit to sample and hold a input signal from a input stage. The S/H circuit includes a switch, a capacitor, and an operational amplifier. The S/H circuit samples and holds the input signal by switching. One terminal of the capacitor is connected to an input terminal of the operational amplifier, and the other terminal of the capacitor is connected to either the input stage which supplies the input signal or an output terminal of the operational amplifier through the switch.
The other terminal of the capacitor is connected to the input stage through the switch during sampling the input signal (hereinafter, referred to as “sample mode”). The capacitor is charged according to a voltage of the input signal from the input stage. On the other hand, the other terminal of the capacitor is connected to the output terminal of the operational amplifier holding the input signal (hereinafter, referred to as “hold mode”). During the hold mode, the capacitor keeps to hold the electric charge which is charged in the sample mode. The sample mode and the hold mode are switched alternately in the S/H circuit. It means that the S/H circuit samples and holds the input signal periodically.
A pipeline analog-to-digital converter (hereinafter, referred to as “pipeline A/D converter”) includes the S/H circuit and cascaded convert stages. Each convert stage has a multiplying digital-to-analog converter (hereinafter, referred to as “MDAC”). The MDAC is also one of the S/H circuits. The MDAC has almost same circuit architecture as the S/H circuit, which includes a switch, a capacitor, and an operational amplifier. The MDAC samples and holds an analog input signal from a previous convert stage as same as the S/H circuit. In addition to the MDAC, each convert stage also has a comparator to convert the analog input signal to a digital input signal.
Both the S/H circuit in the pipeline A/D converter and the S/H circuit in each convert stage (MDAC) realize a sampling of the input signal by charging the capacitor. For example, the operational amplifier in the MDAC of a convert stage is used to charge the capacitor in the MDAC of the next convert stage. It is known that the consumption power of the operational amplifier is relatively large in the total consumption of the pipeline A/D converter.
Because the S/H circuit in the pipeline A/D converter and the S/H circuit in each convert stage (MDAC) sample and hold the input signal continuously, the electric charge which have been held during the hold mode may still remain in the capacitor when the sample mode starts. Therefore, in each sample mode, the capacitor may be charged or discharged an amount of electric charge according to a voltage of the input signal which has a range from minimum to maximum or from maximum to minimum.
One of the conventional pipeline A/D converters is disclosed by K. Honda et Al. “A 14b Low-power Pipelined A/D Converter Using a Pre-charging Technique”, Dig. Symp. VLSI Circuits, pp. 196-197, June 2007. In this reference, a pipeline A/D converter does not sample and hold an input signal continuously, and discharge the electric charge which has been held in the capacitors before sampling the input signal. Since the pipeline A/D converter discharge the electric charge to half amount of the maximum capacitance of each capacitor once, it may not need to charge from 0 volt to maximum voltage or discharge from maximum voltage to 0 volt in the next sample mode. This means the pipeline A/D converter may charge or discharge only half amount of the maximum capacitance of each capacitor. Therefore, the pipeline A/D converter can decrease amount of the electric charge which is required to charge to each capacitor at once in the sample mode.
However, the pipeline A/D converter in the reference needs a time to discharge the electric charge from the capacitors in addition to the time to be required for sampling and holding the input signal. Therefore, the time for sampling and holding is shortened to keep the time for discharging the electric charge. As a result, the capacitors have to discharge the electric charge in a short time before sampling the input signal.